1 of 10 093099 features 30 khz to 100 mhz output frequencies user-programmable on-chip dividers (from 1- 513) user-programmable on-chip prescaler (1, 2, 4) no external components 0.5% initial tolerance 3% variation over temperature and voltage single 5v supply frequency options part no. max o/p freq. ds1065-100 100.000 mhz ds1065-80 80.000 mhz ds1065-66 66.667 mhz ds1065-60 60.000 mhz pin assignment pin description to-92 1 i/o - input/output 2 v cc - power supply 3 gnd - ground description the ds1065 is a fixed frequency oscillator requiring no external components for operation. numerous operating frequencies are possible in the range of approximately 30 khz to 100 mhz through the use of an on-chip programmable prescaler and divider. the ds1065 features a master oscillator followed by a prescaler and then a programmable divider. the prescaler and programmable divider are user-programmable with the desired values being stored in nonvolatile memory. this allows the user to buy an off the shelf component and program it on site prior to board production. design changes can be accommodated easily by simply programming different values into the device (or reprogramming previously programmed devices). the ds1065 is shipped from the factory configured for half the maximum operating frequency. contact the factory for specially programmed devices. the ds1065 features a dual-purpose input/output pin. if the device is powered up in program mode this pin can be used to input serial data to the on-chip registers. after a write command this data is stored in nonvolatile memory. when the chip is subsequently powered up in operating mode these values are automatically restored to the on-chip registers and the input/output pin becomes the oscillator output. the ds1065 is available in to-92 (3 lead) package, allowing the generation of a clock signal easily, economically and using minimal board area. ds1065 econoscillator/divider preliminary www.dalsemi.com 1 2 3 bottom view dallas ds1065 1 2 3
ds1065 2 of 10 block diagram figure 1 part no. suffix intosc frequency -100 100.000 mhz -80 80.000 mhz -66 66.667 mhz -60 60.000 mhz
ds1065 3 of 10 pin descriptions input/output pin (in/out): this pin is the main oscillator output, with a frequency determined by clock reference, m and n dividers. except in programming mode this pin is always an output and will be referred to as ?out?. in programming mode this pin will be referred to as ?in?. user-programmable registers the following registers can be programmed by the user to determine device operating frequency and mode of operation. details of how these registers are programmed can be found in a later section; in this section the function of the registers are described. the register settings are nonvolatile, the values being stored automatically in eeprom when the registers are programmed. note: the register bits cannot be used to make frequency changes on the fly. changes can only be made by powering the device up in ?programming? mode. for them to be become effective the device must then be powered down and powered up again in ?operation? mode. for programming purposes the register bits are divided into two 9-bit words; the ?mux? word determines mode prescaler values and the ?div? word sets the value of the programmable divider. mux word figure 2 (msb) (lsb) 0* 0* 0* 1* 1* m msel div1 0* *these bits must be set to the indicated values div1 this bit allows the master clock to be routed directly to the output (div1=1). the n programmable divider is bypassed so the programmed value of n is ignored. the frequency of the output (f out ) will be intclk or extclk depending on which reference has been selected. if the internal clock is selected the m prescaler is also bypassed (the bit values of msel and m are ignored), so in this case f out = intosc (which also equals mclk and intclk). if div1=0 the prescaler and programmable divider function normally. msel this bit determines whether or not the m prescaler is bypassed. msel =1 will bypass the prescaler. msel =0 will switch in the prescaler (unless overridden by div1=1), with a divide-by number determined by the m bit. m this bit sets the divide-by number for the prescaler. m = 0 results in divide-by-4, m=1 results in divide- by-2. the setting of this bit is irrelevant if either div1=1 or msel =1. table 2 div1 bit msel bit m bit operation 0 0 0 internal oscillator divided by 4*n 0 0 1 internal oscillator divided by 2*n 0 1 x internal oscillator divided by n
ds1065 4 of 10 1 x x internal oscillator divided by 1 div word figure 3 (msb) (lsb) n (9-bits) n these 9 bits determine the value of the programmable divider. the range of divisor values is from 2 to 513, and is equal to the programmed value of n plus 2: table 3 bit values divisor (n) value 000000000 000000001 . . . . . 111111111 2 3 . . . . . 513 power-on reset when power is initially applied to the device supply pin, a power-on reset sequence is executed, similar to that which occurs when the device is restored from a power-down condition. this sequence comprises two stages, first a conventional por to initialize all on-chip circuitry, followed by a stabilization period to allow the oscillator to reach a stable frequency before enabling the output: 1. initialize internal circuitry. 2. enable internal oscillator. 3. set m and n to maximum values. 4. wait approximately 1024 cycles of intosc for the oscillator to stabilize. 5. load m and n programmed values from eeprom. 6. enable out. figure 10
ds1065 5 of 10 programming normally when power is applied to the supply voltage pin the device will enter its normal operating mode, following the power-on reset sequence. however the device can be made to enter a programming mode if a pullup resistor is connected between in/out and the supply voltage pin prior to power-up. the method used for programming is a variant of the 1-wire tm protocol used on a number of dallas semiconductor products. hardware the hardware configuration is shown in the diagram. a bus master is used to read and write data to the ds1065?s internal registers. the bus master may have either an open-drain or ttl-type architecture. figure 11 programming mode is entered by simply powering up the ds1065 with a pullup of approximately 5k w . this will pull the in/out pin above v ih on power-up and initiate the programming mode, causing the ds1065 to internally release the in/out pin after t stab and allow the pullup resistor to pull up the pin to the supply rail and await the master tx reset pulse (see diagram). note: to ensure normal operation any external pullup applied to in/out must be greater than 20 k w in value. this will cause the in/out pin to remain below v ih on power-up, resulting in normal operation at the end of t stab .
ds1065 6 of 10 figure 12 transaction sequence the sequence for accessing the ds1065 via the 1-wire port is as follows: initialization function command transaction/data initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the ds1065. the presence pulse lets the bus master know that the ds1065 is present and is ready to operate. figure 13 function commands once the bus master has detected a presence, it can issue one of the four function commands. all function commands are 8 bits long, and are written lsb first. a list of these commands follows: write div register [01h] this command allows the bus master to write to the ds1065?s div register. read div register [a1h] this command allows the bus master to read the ds1065?s div register.
ds1065 7 of 10 write mux register [02h] this command allows the bus master to write to the ds1065?s mux register. read mux register [a2h] this command allows the bus master to read the ds1065?s mux register. transaction/data immediately following the function command, the 9 data bits are written to or read from the ds1065. this data is written/read lsb first. the following diagrams illustrate the timing. once data transfer is complete a new transaction sequence can be started by re-initializing the device. therefore to program both the div and mux registers two complete transaction sequences are required. read/write time slots the definitions of write and read time slots are illustrated below. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds1065 to the master by triggering a delay circuit in the ds1065. during write time slots, the delay circuit determines when the ds1065 will sample the data line. for a read data time slot, if a 0 is to be transmitted, the delay circuit determines how long the ds1065 will hold the data line low overriding the 1 generated by the master. if the data bit is a 1, the ds1065 will leave the read data time slot unchanged. write 1 time slot figure 14 write 0 time slot figure 15 60 m s = t slot < 120 m s 1 m s = t low1 < 15 m s 1 m s = t rec < 8 60 m s = t low0 < t slot < 120 m s 1 m s = t rec < 8 60 m s = t slot < 120 m s 1 m s = t low1 < 15 m s 1 m s = t rec < 8
ds1065 8 of 10 read data time slot figure 16 return to normal operation when programming is complete, the ds1065 should be powered down. if the pullup resistor on the in/out pin is removed, normal device operation will be restored next time power is applied. default register values unless ordered from the factory with specific register program values, the ds1065 is shipped with the following default register values: div = 0 0000 0000 (programmable divider will divide by two) mux = 0 0011 0100 m = 4 (ignored, see msel ) msel = 1 (m prescaler bypassed) div1 = 0 (n dividers enabled) 60 m s = t slot < 120 m s 1 m s = t lo wr < 15 m s 0 m s = t release < 45 m s 1 m s = t rec < 8 t rdv = 15 m s t su < 1 m s
ds1065 9 of 10 absolute maximum ratings* voltage on any pin relative to ground -1.0v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (t a = 0c to 70c; v cc = 5v 5%) parameter symbol condition min typ max units notes supply voltage v cc 4.75 5 5.25 v high-level output voltage (in/out) v oh i oh = -4 ma, v cc = min 2.4 v low-level output voltage (in/out) v ol i ol = 4 ma 0.4 v high-level input voltage (in/out) v ih 2 v low-level input voltage(in/out) v il 0.8 v high-level input current i ih v ih =2.4v, v cc = 5.25v 1 ua low-level input current i il v il =0,v cc =5.25v -1 ua supply current (active) ds1065-100 ds1065-80 ds1065-66 ds1065-60 i cc c l = 15 pf 35 50 ma ma ma ma
ds1065 10 of 10 ac electrical characteristics (t a = 0c to 70c; v cc = 5v 5%) parameter symbol condition min typ max units notes output frequency tolerance d f o v cc = 5v, t a =25c -0.5 0 +0.5 % combined frequency variation d f o over temp and voltage -3 +3 % power-up time t por + t stab 0.1 1 ms 1 load capacitance (in/out) c l 15 2 pf 2 output duty cycle in/out out0 40 40 60 60 % % jitter j 100 ps 3 notes: 1. this is the time from when v cc is applied until the output starts oscillating. 2. operation with higher capacitance loads may result in reduced output voltage and maximum operating frequency. 3. parameter given is a typical max.
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